Warum habe ich diese komischen Zustandswechsel bei diesem VHDL Code?
Hey, ich habe ein Problem mit meinem VHDL Code, dieser sollte meiner ansicht nach eigentlich super funktiuonnieren, jedoch bekomme ich beim Testen eine komische zurückkopplung auf den Vorherigen Zustand, ich vermute dies hat irgendetwas mit der Ausführungsreihnfolgef zu tun (kann da aber auch falsch liegen). Die Komponenten berechenen sicher alle Ausgänge richtig. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity SpeechAssistant is generic ( CLK_HZ : natural := 10 ); port ( clk : in std_logic; reset : in std_logic; clk_audio : in std_logic; audio_in : in std_logic_vector(23 downto 0) ); end SpeechAssistant; architecture rtl of SpeechAssistant is -- Deklarierungen     type zustand_t is (ERKENNE, KLASSIFIZIERE, STREAME);     signal zustand_ff, zustand_nxt : zustand_t;     --Signale     signal speech_detected : std_logic;     signal wakeword_detected : std_logic;     signal cmd_end : std_logic;     -- Zähler-Signale     signal timer_preset : unsigned(5 downto 0) := (others => '0');     signal timer_start, timer_finished : std_logic; -- PresetDownCounter Komponente     component PresetDownCounter is         generic(             TIMER_BITS : natural := 6         );         port(             clk : in std_logic;             reset : in std_logic;             timer_preset : in unsigned(TIMER_BITS-1 downto 0);             timer_start : in std_logic;             timer_finished : out std_logic         );     end component; --Spracherkenner komponente   component SpeechActivityDetector is     port(         clk : in std_logic;         reset : in std_logic;         clk_audio : in std_logic;         audio_in : in std_logic_vector(23 downto 0);         enable : in std_logic;         speech_detected : out std_logic         );   end component; --Worterkennungskomponente   component WakeWordClassifier is     port(         clk : in std_logic;         reset : in std_logic;         clk_audio : in std_logic;         audio_in : in std_logic_vector(23 downto 0);         enable : in std_logic;         wakeword_detected : out std_logic     );   end component; --Übertragungskomponente   component AudioStreamer is     port(         clk : in std_logic;         reset : in std_logic;         clk_audio : in std_logic;         audio_in : in std_logic_vector(23 downto 0);         enable : in std_logic;         cmd_end : out std_logic     );     end component; begin -- Instanziierung des Timers     timer_inst : PresetDownCounter         generic map (TIMER_BITS => 6)         port map (             clk => clk,             reset => reset,             timer_preset => timer_preset,             timer_start => timer_start,             timer_finished => timer_finished         ); -- Instanzierung ActivityDetector     Detector_inst : SpeechActivityDetector       port map (         clk => clk,         reset => reset,         clk_audio => clk_audio,         audio_in => audio_in,         enable => '1',         speech_detected => speech_detected     ); -- Instanzierung WordClassifier     Classifier_inst : WakeWordClassifier        port map (         clk => clk,         reset => reset,         clk_audio => clk_audio,         audio_in => audio_in,         enable => speech_detected,         wakeword_detected => wakeword_detected     ); --Instanzierung AudioStreamer     Streamer_inst : AudioStreamer        port map (         clk => clk,         reset => reset,         clk_audio => clk_audio,         audio_in => audio_in,         enable => wakeword_detected,         cmd_end => cmd_end     ); --Prozess für den Zustandswechsel process (clk, reset)   begin     if reset = '1' then       zustand_ff <= ERKENNE;     elsif rising_edge(clk) then       zustand_ff <= zustand_nxt;     end if;   end process; --Prozess für TimerSetzung process (zustand_ff)   begin     case zustand_ff is       when KLASSIFIZIERE =>         timer_preset <= to_unsigned(3 * 10, 6);       when STREAME =>         timer_preset <= to_unsigned(5 * 10, 6);       when ERKENNE =>         timer_preset <= (others => '0');     end case; end process; --Prozess für Zustandslogik process (zustand_ff, timer_finished, speech_detected, wakeword_detected, cmd_end)   begin     zustand_nxt <= zustand_ff;     timer_start <= '0';          case zustand_ff is       when ERKENNE =>         if speech_detected = '1' then           zustand_nxt <= KLASSIFIZIERE;         else           zustand_nxt <= ERKENNE;         end if;       when KLASSIFIZIERE =>         timer_start <= '1';         if timer_finished = '1' then           zustand_nxt <= ERKENNE;         elsif wakeword_detected = '1' then           zustand_nxt <= STREAME;           timer_start <= '0';         end if;     when STREAME =>       timer_start <= '1';       if timer_finished = '1' then         zustand_nxt <= ERKENNE;       elsif cmd_end = '1' then         zustand_nxt <= ERKENNE;       end if;     end case; end process; end architecture rtl
